Adaptively Speculative Execution for Wide-Issue Superscalar Processors

Abstract In the past, a scheme of Adaptive Branch Trees (ABT) has been proposed for adaptively keeping track of alternative branch paths and to speculatively execute the code on the most likely path with constrained hardware resources. In this paper, we combine the ABT concept with the instruction prefetch by realizing an ABT table to prefetch the most likely path of execution stream codes so as to reducing instruction cache miss penalty. Then, we focus on the speculative execution with ABT scheme. We will take the advantage of the property of ABT to exploit execution parallelism. We propose a register renaming mechamism to ensure that the values of registers are generated and accessed to keep data consistency and control dependency under dynamic out-oforder execution.